Investigation of Portable Event Based Monte Carlo Transport Using the Nvidia Thrust Library

Power consumption considerations are driving future high performance computing platforms toward many-core computing architectures. The Trinity machine to become available at Los Alamos National Laboratory in 2016 will use both Intel Xeon Haswell processors and Intel Xeon Phi Knights Landing many integrated core (MIC) architecture coprocessors. The Sierra machine to be available at Lawrence Livermore National Laboratory beginning in 2018 will use an IBM PowerPC architecture along with Nvidia graphics processing unit (GPU) architecture accelerators. As a result of these different advanced architectures, the computing landscape for the upcoming years is complex. Traditional approaches to Monte Carlo transport do not work efficiently on these new computing platforms. MIC architectures require vectorization to operate efficiently, vectorization is difficult to achieve in Monte Carlo transport. GPU architectures require additional code to explicitly use the hardware, requiring significant code changes or hardware specific branches in the source code. A significant challenge for Monte Carlo transport projects is to simultaneously support efficient versions of simulation codes for both the current generation and the different advanced computing architectures within a single source code base. In order to address these issues, two important changes are typically made: a new algorithmic approach to solving Monte Carlo transport, and explicit use of the GPU hardware in software. In this paper, we describe initial research investigations of an event based Monte Carlo transport algorithm [1] implemented using the Nvidia Thrust library [2] on a GPU for a Monte Carlo test code. The event based algorithm targets many-core architectures by increasing SIMD (single instruction multiple data) parallelism, while Thrust provides portable performance by allowing one source code base to compile code targeted for both CPUs and GPUs